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270 lines
7.7 KiB
C
270 lines
7.7 KiB
C
/*
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Vendor Reset - Vendor Specific Reset
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Copyright (C) 2020 Geoffrey McRae <geoff@hostfission.com>
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Copyright (C) 2020 Adam Madsen <adam@ajmadsen.com>
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free Software
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Foundation; either version 2 of the License, or (at your option) any later
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version.
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This program is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/delay.h>
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#include "vendor-reset-dev.h"
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#include "amd.h"
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#include "common.h"
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#include "firmware.h"
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#include "amdgpu_discovery.h"
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#include "smu_v11_0.h"
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#include "mp/mp_11_0_offset.h"
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#include "mp/mp_11_0_sh_mask.h"
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#include "nbio_2_3_offset.h"
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#include "psp_gfx_if.h"
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#include "nv.h"
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#define log_prefix "Navi10/12/14: "
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#define nv_info(fmt, arg...) pci_info(dev->pdev, log_prefix fmt, ##arg)
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#define nv_warn(fmt, arg...) pci_warn(dev->pdev, log_prefix fmt, ##arg)
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#define nv_err(fmt, arg...) pci_err(dev->pdev, log_prefix fmt, ##arg)
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extern bool amdgpu_get_bios(struct amd_fake_dev *adev);
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static int amd_navi10_reset(struct vendor_reset_dev *dev)
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{
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struct amd_vendor_private *priv = amd_private(dev);
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struct amd_fake_dev *adev;
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int ret = 0, timeout;
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u32 sol, smu_resp, mp1_intr, psp_bl_ready, tmp, offset;
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adev = &priv->adev;
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ret = amd_fake_dev_init(adev, dev);
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if (ret)
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return ret;
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ret = amdgpu_discovery_reg_base_init(adev);
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if (ret < 0)
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{
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nv_info("amdgpu_discovery_reg_base_init failed, using legacy method\n");
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switch (dev->info)
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{
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case AMD_NAVI10:
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navi10_reg_base_init(adev);
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break;
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case AMD_NAVI12:
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navi12_reg_base_init(adev);
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break;
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case AMD_NAVI14:
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navi14_reg_base_init(adev);
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break;
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default:
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pci_err(dev->pdev, "Unknown Navi type device: [%04x:%04x]\n", dev->pdev->vendor, dev->pdev->device);
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return -ENOTSUPP;
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}
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}
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if (!amdgpu_get_bios(adev))
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{
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nv_err("amdgpu_get_bios failed: %d\n", ret);
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ret = -ENOTSUPP;
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goto free_adev;
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}
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ret = atom_bios_init(adev);
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if (ret)
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{
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nv_err("atom_bios_init failed: %d\n", ret);
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goto free_adev;
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}
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/* it's important we wait for the SOC to be ready */
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for (timeout = 100000; timeout; --timeout)
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{
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sol = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
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if (sol != 0xFFFFFFFF && sol != 0)
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break;
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udelay(1);
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}
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if (sol == ~1L)
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{
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nv_warn("Timed out waiting for SOL to be valid\n");
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/* continuing anyway because sometimes it can still be reset from here */
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}
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nv_info("bus reset disabled? %s\n", (dev->pdev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) ? "yes" : "no");
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/* collect some info for logging for now */
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smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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mp1_intr = (RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff)) &
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT;
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psp_bl_ready = !!(RREG32(mmMP0_SMN_C2PMSG_35) & 0x80000000L);
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nv_info("SMU response reg: %x, sol reg: %x, mp1 intr enabled? %s, bl ready? %s\n",
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smu_resp, sol, mp1_intr ? "yes" : "no",
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psp_bl_ready ? "yes" : "no");
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/* okay, if we're in this state, we're probably reset */
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if (sol == 0x0 && !mp1_intr && psp_bl_ready)
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goto free_adev;
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/* this tells the drivers nvram is lost and everything needs to be reset */
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nv_info("Clearing scratch regs 6 and 7\n");
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WREG32(adev->bios_scratch_reg_offset + 6, 0);
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WREG32(adev->bios_scratch_reg_offset + 7, 0);
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/* it only makes sense to reset mp1 if it's running
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* XXX: is this even necessary? in early testing, I ran into
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* situations where MP1 was alive but not responsive, but in
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* later testing I have not been able to replicate this scenario.
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*/
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if (smu_resp != 0x01 && mp1_intr)
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{
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nv_info("MP1 reset\n");
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WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
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1 & MP1_SMN_PUB_CTRL__RESET_MASK);
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WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
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1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
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nv_info("wait for MP1\n");
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for (timeout = 100000; timeout; --timeout)
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{
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tmp = RREG32_PCIE(MP1_Public |
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(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
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if ((tmp &
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
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break;
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udelay(1);
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}
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if (!timeout &&
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!((tmp & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
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MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT))
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{
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nv_warn("timed out waiting for MP1 reset\n");
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}
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smu_wait(adev);
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smu_resp = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
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nv_info("SMU resp reg: %x\n", tmp);
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}
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/*
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* again, this only makes sense if we have an SMU to talk to
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* some of these may fail, that's okay. we're just turning off as many
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* things as possible
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*/
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if (mp1_intr)
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{
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smu_wait(adev);
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/* disallowgfx_off or something */
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nv_info("gfx off\n");
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x2A);
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smu_wait(adev);
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/* stop SMC */
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nv_info("Prep Reset\n");
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0x00);
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, 0x00);
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/* PPSMC_MSG_PrepareMp1ForReset */
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WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, 0x33);
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smu_wait(adev);
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}
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nv_info("begin psp mode 1 reset\n");
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amdgpu_atombios_scratch_regs_engine_hung(adev, true);
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pci_save_state(dev->pdev);
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/* check validity of PSP before reset */
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nv_info("PSP wait\n");
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x8000FFFF, false);
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if (tmp)
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nv_warn("timed out waiting for PSP to reach valid state, but continuing anyway\n");
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/* reset command */
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nv_info("do mode1 reset\n");
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WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_MODE1_RST);
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msleep(500);
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/* wait for ACK */
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nv_info("PSP wait\n");
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offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
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tmp = psp_wait_for(adev, offset, 0x80000000, 0x80000000, false);
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if (tmp)
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{
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nv_warn("PSP did not acknowledger reset\n");
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ret = -EINVAL;
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goto out;
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}
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nv_info("mode1 reset succeeded\n");
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pci_restore_state(dev->pdev);
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for (timeout = 100000; timeout; --timeout)
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{
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tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
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if (tmp != 0xffffffff)
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break;
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udelay(1);
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}
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nv_info("memsize: %x\n", tmp);
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/*
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* this takes a long time :(
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*/
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for (timeout = 100; timeout; --timeout)
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{
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/* see if PSP bootloader comes back */
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if (RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L)
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break;
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nv_info("PSP bootloader flags? %x, timeout: %s\n",
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RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35), !timeout ? "yes" : "no");
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msleep(100);
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}
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if (!timeout && !(RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35) & 0x80000000L))
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{
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nv_warn("timed out waiting for PSP bootloader to respond after reset\n");
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ret = -ETIME;
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}
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else
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nv_info("PSP mode1 reset successful\n");
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pci_restore_state(dev->pdev);
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out:
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amdgpu_atombios_scratch_regs_engine_hung(adev, false);
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free_adev:
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amd_fake_dev_fini(adev);
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return ret;
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}
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const struct vendor_reset_ops amd_navi10_ops =
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{
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.pre_reset = amd_common_pre_reset,
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.reset = amd_navi10_reset,
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.post_reset = amd_common_post_reset,
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};
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